The present invention relates to nonvolatile semiconductor memories, and more particularly to nonvolatile semiconductor memories with a NAND logic memory cell structure.
A nonvolatile semiconductor memory such as an EEPROM (Electrically Erasable and Programmable Read Only Memory) or MROM (Mask Read Only Memory) has a memory cell structure based on NOR logic or NAND logic. A NAND logic structure requires fewer select transistors per cell and fewer contact holes between bit lines; accordingly, a NAND logic memory cell structure is used in most nonvolatile semiconductor memories. A typical NAND logic memory cell consists of a plurality of unit memory strings each having a memory cell transistor for storing data and string select means for selecting a unit memory string in which a desired memory cell transistor is located. U.S. Pat. No. 4,142,176, issued on Feb. 27, 1979 discloses a nonvolatile semiconductor memory having a cell array wherein string select means and a NAND logic memory cell transistor are serially connected. Specifically, in a plurality of unit memory strings constituting a cell array, a string select transistor for selecting a memory string is serially connected to a plurality of series-connected memory cell transistors for storing data, and a power supply line and a bit line are respectively connected to both ends of the string select transistor and the memory cell transistor. During a data access operation, a voltage is supplied to the bit line, a string operation of the string select transistor results in a selection of and the memory cell transistor on the selected memory string. However, in such a NAND logic memory cell structure, one unit memory string is connected to one bit line. This arrangement is not suitable for high integration of a memory circuit due to the pitch necessarily required between bit lines.
To overcome that disadvantage, an improved structure has been proposed in which two unit memory strings are connected to one bit line, as disclosed in Japanese Patent Provisional Publication No. 2-65170. Referring to FIG. 1, two parallel unit memory strings are connected to a bit line BL selected by a column decoder within a chip. String select transistors MS10A, MS11A, MS20A and MS21A selected by a row decoder and n memory cell transistors M10A, . . . M1nA, M20A, . . . M2nA driven by word lines WL0, . . . , WLn are serially connected to the memory string. Since two string select transistors are connected to one unit memory string, it is possible to independently select two unit memory strings connected to one bit line. During reading and writing operations, only one of two string select transistors is set to logic xe2x80x9chighxe2x80x9d by an address applied to the chip and simultaneously only one selected word line out of word lines WL0, . . , WLn is set to logic xe2x80x9clowxe2x80x9d. For example, if string select line SS0 and word line WL0 are selected by a decoded address, the string select lines SS0 and SS1 are respectively set to logic xe2x80x9chighxe2x80x9d and xe2x80x9clowxe2x80x9d, and the word line WL0 is set to logic xe2x80x9clowxe2x80x9d. All other word lines are set to logic xe2x80x9chighxe2x80x9d. The string select transistor MS10A constituting the memory string is an enhancement transistor having a positive threshold voltage and the string select transistor MS11A is a depletion transistor having a negative threshold voltage. The memory cell transistors are either enhancement or depletion transistors according to a programmed state. Therefore, the string select transistors MS10A, MS11A and MS20A are turned on and the string select transistor MS21A is turned off. The bit line BL0 is electrically connected to a connecting point A, and insulated from a connecting point B by the string select transistor MS21A. Since it is an enhancement transistor, the memory cell transistor M1nA becomes conductive irrespective of the programmed state and connected or disconnected to a ground connecting point C depending on the threshold voltage of the memory cell transistor M10A whose gate is connected to the word line WL0. If the memory cell transistor M10A is a depletion transistor, the bit line BL0 is electrically connected to the ground connecting point C. If the memory cell transistor M10A is an enhancement transistor, the bit line BL0 is insulated from the ground connecting point C. The voltage of the selected memory cell is typically read out by a sense amplifier (not shown) connected to the bit line.
Referring still to FIG. 1, the voltage level of the word lines WL0, . . . , WLn is set to logic xe2x80x9chighxe2x80x9d during a stand-by state. Hence, a gate film of the memory cell transistor may break due to the stress generated by this voltage level, defects in a manufacturing process, or the like. In a very large scale semiconductor integrated circuit including minimally-sized memory cells, this possibility is increased. When defects occur in memory cell transistors, even if the defects are repaired by an error correcting code (ECC) circuit for example, problems such as increased current consumption resulting from the current path formed during the stand-by state from the word line voltage applied to the destroyed gate film to ground.
Another conventional nonvolatile semiconductor memory having a NAND logic cell structure is disclosed in Korean Patent Application No. 1991-6569, filed Apr. 24, 1991. Referring now to FIG. 2, switching means MG1B, MG2B, . . . are controlled by a ground select signal GSS as a decoding signal. By the switching means MG1B, MG2B, . . . , each memory string is selectively connected to a ground connecting point. That is, the switching means MG1B, MG2B, . . . repairs the increase of current during the stand-by state of a memory device. Even if a transistor selected by word lines WL0, . . . , WLn, bit lines BL0, BL1, . . , and first and second string select signals SS0 and SS1 forms a current path to the ground connecting point during the stand-by state, since switching transistors MG1B, MG2B, . . . are turned off and on by the ground select signal GSS during the stand-by operation and reading operation, respectively, the increase of the current caused by the breakdown of the gate film of the transistor during the stand-by operation of the chip is prevented. Though not shown in the drawing, the ground select signal GSS is generated by a decoding operation of a row decoder. During a select operation of the memory cell transistor, the ground select signal GSS is logic xe2x80x9chighxe2x80x9d, and during other operation including the stand-by operation, the ground selected signal GSS is logic xe2x80x9clowxe2x80x9d.
However, as the packing density of semiconductor integrated circuits increases, the separation between metal bit lines formed on the semiconductor substrate of a chip decreases significantly. Therefore, a bridge phenomenon, or short, caused by a particle during a manufacturing process may frequently occur, and is difficult to repair. In semiconductor memories 64 Mbits (mega: 106) or 128 Mbits in size, the bit line is generally formed with metal, and the bridge phenomenon is a great obstacle in the manufacturing process.
It is therefore an object of the present invention to provide a reliable nonvolatile semiconductor memory suitable for increased chip packing density.
It is another object of the present invention to provide a low power consumption nonvolatile semiconductor memory suitable for high integration.
It is yet another object of the present invention to provide a nonvolatile semiconductor memory which prevents a bridge phenomenon between metals in a high integration chip.
It is still another object of the present invention to provide a nonvolatile semiconductor memory with a NAND cell array structure which prevents unnecessary current consumption during a stand-by operation.
It is still yet another object of the present invention to provide a nonvolatile semiconductor memory with a NAND cell array structure for facilitating design.
It is a further object of the present invention to provide a nonvolatile semiconductor memory with a NAND cell array structure which prevents current consumption during a stand-by state due to the breakdown of a gate film of a cell transistor and which is easily integrated with a higher packing density.
In accordance with one aspect of the present invention, a nonvolatile semiconductor memory having a cell array consisting of a plurality of unit memory strings in the row and column directions, a plurality of memory cells whose channels are serially connected constituting one unit memory string, includes at least two string select transistors connected in series to one end of the unit memory string and controlled by a string select signal, and at least two ground select transistors connected in series to the other end of the unit memory string and controlled by a ground select signal; the memory is thus provided with a string select function and a ground select function. In the nonvolatile semiconductor memory embodied according to the present invention, one bit line is connected to two unit memory strings or four unit memory strings. It is preferable to determine the number of unit memory strings connected to one bit line based on the degree of chip integration, the art, etc. Meanwhile, at least two ground select transistors (hereinafter the term xe2x80x9cground select transistorxe2x80x9d is used for descriptive convenience and it should be noted that a ground select transistor has a ground select function as well as a string select function) are series connected to one unit memory string prevent a current path from being formed during nonconducting conditions when a particular memory string is not selected.